Sijin C Johnson

About Sijin C Johnson

Good knowledge on Digital Design in Gate level and knowledge in CMOS…

Experience

1. Trainee

   Maven Silicon

   Aug 2018 — Present · Bengaluru, IN

   Currently working as a Design and Verfication trainee at Maven Silicon.During this period i have learnt Digital Design,RTL coding using Verilog,System Verilog for Verification and also Universal Verification Methodology.** Projects Completed **[1] AHB2APB Bridge IP Core Verification : HVL: System Verilog TB Methodology: UVM EDA Tool: Riviera Pro – Aldec Description : The AHB to APB bridge is an AHB slave which works as an interface between the high speed AHB and the low performance APB buses.Responsibilities: Architected the class based verification environment in UVM. Defined Verification Plan Verified the RTL module with UVM Test Bench with different test scenarios like singleREAD, WRITE & Burst READ, WRITE with different burst lengths. Generated functional and code coverage for the RTL verification sign-off.[2] Router 1x3 – RTL design: HDL: Verilog EDA Tool: Xilinx ISE,Riviera ProDescription: The router accepts data packets on a single 8-bit port and routes them to one of the three output channels (channel0, channel1, channel2).