Sidlingesha G
Lead Layout Engineer at Qualcomm India Pvt. Ltd.
- Role
- Lead Layout Engineer at Qualcomm
- Location
- Bengaluru, KA, IN
- LinkedIn followers
- 500 followers
About Sidlingesha G
Currently working in RF Layout design in Qualcomm India Pvt ltd. Previously I was working in Analog Design Domain at Sankalp Semiconductor with specialization in Analog Layout design & verification. I have completed Bachelor of Engineering in Electrical & Electronics from Cambridge Institute of Technology in 2015. My Technical skills include:1. Analog Layout (Cadence virtuoso)2. Digital Layout (Cadence virtuoso)3. Automation (Skill)4. Design verification including DRC, LVS, RCX in Assura & Calibre.5. Basic Analog circuit Design6. Basic Digital circuit Design7. Basic programming Language C, Java, HTML, CSS, Javascript
Experience
Lead Layout Engineer
Dec 2025 — Present · Bengaluru, IN
Education
Cambridge Institute of Technology
Engineer’s Degree, Electrical and Electronics Engineering
2011 — 2015
Indian Institute of Technology, Madras
Master of Technology - MTech, Integrated circuits and systems
Govt High School for Boys, Kottur
High School, sslc
2006 — 2009
Kottureshwara College, Kottur.
PUC, PCMB
2009 — 2011
Skills
- Java
- Analog Layout Design
- Digital Layout Design
- Skill Automation
- C
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