Siddu Aski
Analog Layout Engineer
- Role
- Graduate Trainee at Bharat Electronics Limited
- Location
- Bengaluru, KA, IN
- LinkedIn followers
- 500 followers
About Siddu Aski
I have done projects on Digital Standard Cells Layouts and creating p-cells, Full custom those are the basic digital gates like -AND,OR,NOT,NAND,NOR,EXNOR,EXOR,DFF.•These standard cells are maintained at DRC and LVS clean.•I know CMOS fundamentals and FinFET technologies.•I have a knowledge on \"Schematic Design, Floor planning, Placement & Routing And Timing Analysis\". Tool experience in VIRTUOSO XL.Able to do layouts from scratch.• Hands on experience in IC verification terminology DRC, LVS, compatibility rules.
Experience
Graduate Trainee
Aug 2025 — Present · Bengaluru, IN
Education
BLDEAs College of Engg. & Technology, BIJAPUR
Electrical and Electronics engineering , .
byMerit
Analog layout design
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