Siddharth Shukla
Design Engineering Architect at Cadence Design Systems
- Role
- Design Engineering Architect at Cadence
- Location
- Bengaluru, KA, IN
- LinkedIn followers
- 500 followers
EngineeringView LinkedIn profile
About Siddharth Shukla
Specialties: PCI Express Gen 6.0,5.0,4.0,3.0,2.0,1.0, Currently involved in and focused on Front end RTL Design Using Verilog. Also Involved in Lint/CDC, Static timing Analysis, Synthesis. Prior Experience in Design Verification.
Experience
Design Engineering Architect
Jul 2024 — Present · Bengaluru, IN
Education
Sarvodaya Pre University College
PCME
2002 — 2004
Birla Institute of Technology and Science, Pilani
Bachelor of Engineering, Electronics and Instrumentation
2004 — 2008
Skills
- System Verilog
- Soc
- Fpga
- Asic
- Tcl
- Functional Verification
- Vlsi
- Pcie
- Eda
- Modelsim
- Static Timing Analysis
- Systemverilog
- Rtl Design
- Verilog
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