Siddharth Sharma

WORK HISTORY

EDUCATION

SKILLS

ABOUT SIDDHARTH SHARMA

Technical Skills:• Delivered multiple subsystem level and IP level verification project from scratch as a Lead and module owner.• Leading MDFI (Multi Die Fabric Interconnect) Subsystem Verification with eight members Team in Intel.• Experience in verifying Vector Processor from scratch.• Good Verification Experience in standard protocols like DDR, Ethernet, MCAN, IPSEC, Macsec etc.• Experience in CDC (Clock Domain Crossing) DV using Cadence’s Jasper Gold Metastability Injection Tool. • Functional Coverage driven verification with Single Testcase methodology by extensive use of Command Line Arguments (CLA). • Good exposure to various interfacing protocols like: AXI3, AXI4, AHB, APB, SPI, UART and I2C. • Expertise in HVL like System Verilog & Verification methodology: UVM. • Strong and consistent hands on experience in verification of block/subsystem/Chip for various SOCs & ASICs. Which includes - Define Verification Strategies. Creating test plan and coverage plan. Development of testbench & environments from scratch using system verilog & UVM. Define and code verification components like agents, checkers, monitors, scoreboards, coverage models etc. • Experience in System verilog Assertions and Coverage. • Scalable & Modular approach to make verification components reusable. Implemented Agent Layering Approach to enhance reusability. • Verification of Time Sliced Architecture based designs. • Verification environment Scalability using Parameterized environments, agents & interfaces.