Siddharth Pethe

CPU Design Verification Engineer at Intel Corporation

Role
Cpu Design Verification Engineer at Intel
Location
Bengaluru, KA, IN
LinkedIn followers
500 followers

About Siddharth Pethe

Post Graduate Diploma in Integrated VLSI and Embedded System Design from Thakur Institute of Career Advancement, CDAC ACTS, MumbaiAcquainted with various EDA Tools like Xilinx ISE v8.2, v9.1, v14.7, Modelsim v10 & Tanner EDA v13Possess VLSI domain skills such as Verilog, System Verilog with UVM, Circuit Simulation, CMOS Concepts, Static Timing Analysis Concepts.Acquainted with protocols such as I2C, SPI, APB, AHB. Proficient in ASIC and FPGA Design Flow with understanding of Circuit Simulation using SPICE Coding Published the paper on ‘Design of Ternary D Flip-Flop using Neuron MOSFET’ in IOSR Journal of VLSI & Signal Processing Vol. 5, Issue 2, Ver. II, PP.(35-39), E-ISSN: 2319 – 4200 and P-ISSN No. 2319 – 4197.Executed various projects on ‘Design of Ternary SRAM Cell using Reconfigurable CMOS’, ‘Electronic Weighing Machine’ and ‘LCD Interfacing’, ‘Traffic Light Controller’, ‘Verification of Dual port RAM’. A go-getter with strong communication, coordination, & analytical skills

Experience

  1. Cpu Design Verification Engineer

    Intel

    Nov 2019 — Present · Bengaluru, IN

Education

  • Sardar Patel High school

    S.S.C

    2005

  • Thakur Institute of Career Advancement

    PG-Diploma, Embedded and VLSI engg

    2011 — 2012

  • Babasaheb Gawde Institute of Technology

    Diploma, Electronics and Telecommunication Engineering

    2005 — 2008

  • Tulsiramji Gaikwad-Patil College of Engg, & Tech

    Bachelor, Electronics Engineering

    2008 — 2011

  • Vel Tech Dr.RR & Dr. SR Technical University

    Master of Technology (MTech), VLSI

    2013 — 2015

Skills

  • Very-Large-Scale Integration (Vlsi)
  • System Verilog
  • Xilinx
  • Systemverilog
  • Matlab
  • Uvm
  • Xilinx Ise 14.5
  • Cadence Virtuoso
  • Static Timing Analysis
  • Digital Electronics
  • Field-Programmable Gate Arrays (Fpga)
  • Vlsi
  • Linux
  • Modelsim
  • Vhdl
  • Questasim
  • C
  • Embedded Systems
  • Fpga
  • Asic
  • Integrated Circuit Design
  • Memory
  • Verilog
  • Microcontrollers
  • Cmos
  • Spice
  • Embedded C
  • Application-Specific Integrated Circuits (Asic)
  • Xilinx Ise
  • I2c
  • C++
  • Multisim
  • Universal Verification Methodology

Find verified contacts for anyone on LinkedIn

Unifers gives sales teams verified emails and direct dials, enriched profiles, and outreach that lands in the inbox.

Free plan included · No credit card required

This profile is compiled from publicly available professional sources. Unifers is not affiliated with or endorsed by LinkedIn. Request removal of this profile.

Siddharth Pethe — Cpu Design Verification Engineer at Intel in Bengaluru, KA, IN | Unifers