Siddharth Kandpal
ASIC/FPGA Video Processing @ Crestron | MSc in Electrical Engineering
- Role
- Electronics Engineer at Crestron Electronics
- Location
- Jersey City, NJ, US
- LinkedIn followers
- 500 followers
About Siddharth Kandpal
As far as I can recall, my interests towards an MBA morphed into an augmented love…
Experience
Electronics Engineer
Aug 2023 — Present · Rockleigh, NJ, US
Verification of low-level signals/pins connected to the top level using SystemVerilog via VCS/QuestaSim. Designed a UART and a dynamic memory SPI module for for simulation purposes with the aim of receiving signals coming in from our processor. Successfully read characters and strings over the UART and the SPI. Deployed the latest (as of today) FPGA build release for the company’s 36x series encoder and decoder system. Curated the particular FPGA from the given flavors (specifications and features). Successfully built, compiled and managed to boot the RBF files on to the FPGA using SSH, streaming audio and video over IP. Implemented I/O mapping for F2S and S2F (FPGA-><- SOC) signals through the avalon MM interface. Also I/O coverage for SII9396, UART4\'s, and 16550 along with NIOS message FIFO\'s. Covered SCDC and EDID functionality.
Education
Narsee Monjee Institute of Management Studies, Mumbai
Master of Business Administration - MBA, Marketing
New York University
Master of Science - MS, Electrical Engineering
SVKM's NMIMS Mukesh Patel School of Technology Management & Engineering
Bachelor of Engineering - BE, Electrical, Electronics and Communications Engineering
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