Siddhant Kukade

Experience

1. Hardware Designer

   Intel

   Jul 2023 — Present · Bengaluru, IN

   Physical Design (STA & PNR): Led timing closure for >5GHz CPU designs on Intel 18A/16A and TSMC N2 process nodes. Managed I/O timing budgets to minimize min-max contention and performed STA and ECOs for high-quality partition closure. Developed Python/TCL scripts and innovative strategies to resolve timing violations, particularly hold and setup. Reduced crosstalk using Synopsys NanoTime and cut core leakage power by 0.5% with PTPX and Fusion Compiler. Optimized inter-partition bus performance by analyzing micro-architectural bottlenecks using Synopsys PrimeTime. Implemented thermal-aware algorithms for routing, congestion control, and port placement to improve timing and power. Collaborated with global Intel teams to achieve optimal results.Architecture & RTL Design: Gained expertise in x86 architecture, focusing on the Out-of-Order Execution Unit and Fused-Multiply-Add (FMA) unit. Enhanced floating-point FMA operations by identifying and resolving discrepancies in the RTL code. Proposed RTL optimizations that yielded significant power efficiency improvements, comparable to ARM architectures.