Siddesh Patil

About Siddesh Patil

I am deeply curious about Advanced Computer architectures, and I love the puzzle of Verifying them.Currently, I’m pursuing my M.S. in ECE at Portland State University, specializing in Computer Architecture and Verification/ Validation. I am actively seeking full-time roles in Design Verification and Silicon Validation starting in June 2026.Throughout my internships, I’ve worked across the full Verification and Validation spectrum: CPU Design Verification: At Tenstorrent, I am verifying an Out-of-Order AI CPU microarchitecture (focusing on ROB, Dispatch, and Scheduling). I build scalable UVM environments and drive verification plans using SVA and constrained-random testing, accelerating workflows by 1.5x through Python automation. Pre-Silicon Validation: At Qualcomm, I debugged Q-DSP (NPU) in Assembly using the T-32 debugger. Worked with LFSR-based Pseudo-Random number generator for memory-restricted regions. I authored atomic-instruction tests to hunt down deadlocks and automated Python flows that cut emulation time and freed up scarce hardware. Architecture & RTL: At Vyoma Systems (IIT Madras) and CASL, I built test plans for the SHAKTI RISC-V SoC, finding critical bugs and driving coverage closure. I also implemented ALRESCHA accelerator modules in Verilog, squeezing ~20% more throughput on sparse matrix workloads.I thrive on the hunt for edge cases and the satisfaction of a green regression dashboard. If your team is building next-generation silicon, I’d love to connect! Core Toolbox:Languages: SystemVerilog, Verilog, C, Assembly (ARM, RISC-V, x-86), PythonMethodologies: UVM, Class-Based Verification, JTAG, Constrained-Random, SVA, Functional/Code CoverageProtocols & Domains: RISC-V, CPU/Vector Architecture, AXI/APB, DDR4/5, Cache Coherence, I2C, SPITools: QuestaSIM, Verdi, Trace-32, Vivado, Linux, Git

Experience

1. Risc-v Cpu Design Verification Intern

   Tenstorrent

   Jan 2026 — Present · Santa Clara, CA, US

   Verifying Out-of-Order AI CPU microarchitecture (ROB, Dispatch, and Scheduling logic) using SystemVerilog Assertions (SVA) and Constrained-Random, with modular, scalable UVM environments for AI hardware.↠ Driving verification Test plans for CPU micro-architecture with targeted test scenarios, Constrained random stimulus, and Coverage.↠ Accelerating verification workflows through automated regression runs, test generation, and Python scripting.

Education

• Father Agnel School

  School

  2018

• Portland State University

  Masters, Electrical and Computer Engineering

• Veermata Jijabai Technological Institute (VJTI)

  Bachelor of Technology - BTech, Electronics