Siddesh Halavarthi Math Revana
Corporate Vice President at AMD India
- Role
- Corporate Vice President at AMD
- Location
- Bengaluru, KA, IN
- LinkedIn followers
- 500 followers
About Siddesh Halavarthi Math Revana
An experienced VLSI professional with a track record of managing Design and Verification of leading edge Memory Controllers, interconnects and CPU Systems.Proficient in setting and delivering on quality goals and aggressive schedules by deploying state-of-the-art design and verification methodologies and techniques. Has authored articles on Assertion Based Verification, Coverage Convergence and Formal Verification Techniques and presented in international conferences too.Specialties: Technical Leadership with emphasis on Quality & ScheduleDesign and Verification of CPU & DDR Systems spanning across func, low-power and performance aspectsACE/CHI/AXI/AHB/APBI BUS and LPDDRx/PCDDRx DDR ProtocolsConstrained Random, Formal Verification and Convergence TechniquesEarly adoption and successful deployment of Portable Stimulus Standard (PSS)UPF based low-power design and validation of complex systems
Experience
Corporate Vice President
Jul 2024 — Present · Bengaluru, IN
Leading India Cores team (CPU team), an extremely passionate group highly focused on delivering industry-leading performance-per-watt CPUs across server, client, and S3 products. Our strength lies in deep expertise across perf modeling, u-arch/RTL, advanced DV, and cutting-edge physical design. Committed to driving excellence across the development lifecycle and shaping the future of energy-efficient, high-performance computing through trusted partnerships with global teams in Zen core innovations
Education
Birla Institute of Technology and Science (BITS), Pilani
Master of Science (MS)
Bapuji institute of engineering and technology
Bachelor of Engineering
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