Shyju Pv

About Shyju Pv

Strategic, technical, and organizational leader with 25+ years of experience driving CPU performance analysis, CPU microarchitecture optimization, and power efficiency for flagship Mobile, Automotive, IoT, Wearables, and Compute platforms.Currently, I lead the CPUSS PnP (Performance and Power) charter for Snapdragon X Elite and custom CPU architectures at Qualcomm. I hold end-to-end ownership of the silicon lifecycle—from early performance modelling to post-silicon performance and power correlation, binning, and HVM readiness. My mission is surgically precise: ensuring every Snapdragon product hits the market with best-in-class power efficiency and a performance profile that defines industry standards. CORE IMPACT & LEADERSHIPSnapdragon X Elite Delivery: Primary sign-off authority for CPU performance, frequency, and power, spanning pre-silicon targets through post-silicon validation.Proven Scale: Delivered 50+ SoCs across compute, auto, and mobile, achieving industry-leading Perf/W and a sustained <5% performance correlation.Organizational Growth: Built the BDC CPU Performance team from inception to 20+ specialized engineers, serving as the global technical authority for PnP sign-off.Executive Influence: Advise senior leadership on performance/power risks and binning strategies, shaping SKU positioning and OEM launch readiness. TECHNICAL TOOLKITCPU Performance & Benchmarking: Expert-level tuning and analysis using SPEC, Geekbench, Antutu, and custom workloads.CPU Microarchitecture: Deep knowledge of Custom & ARMv8/v9, Coherent Interconnects (NoC), DDR5/LPDDR5x, and Cache Hierarchies.Post-Silicon Engineering: Electrical characterization (IDDQ, Leakage, PVT), V-F Curve optimization, Vmin trade-offs, and ATE/SLT correlation to maximize silicon yields.PnP Methodology: Workload characterization, system-level tracing, DVFS, and BTO/MTO sign-off protocols.Software Systems: Linux/Android/Windows on ARM tuning, Energy Aware Scheduler (EAS), and compiler-level performance analysis. MISSION & STRATEGY I bridge the gap between engineering and product strategy. By establishing robust performance modelling and performance correlation strategies, I ensure pre-silicon targets translate into real-world wins. I work with ATE, SLT, and HVV teams to drive the best Vmin/Fmax and silicon yields, balancing aggressive performance bins with manufacturing stability.

Experience

1. Principal Engineer, Manager

   Qualcomm

   Nov 2022 — Present · Bengaluru, IN

   Key Responsibilities & Technical Leadership:End-to-End PnP Governance: Serve as the primary sign-off authority for CPU Performance and Power (PnP) across the silicon lifecycle for Snapdragon X Elite and custom CPU architectures, encompassing BTO/MTO and ES/CS milestones.Performance-Power Correlation: Drive technical strategy for pre-to-post silicon correlation, utilizing empirical models to achieve <5% variance across industry-standard suites (SPEC, Geekbench, Antutu).Silicon Characterization & Binning: Collaborate with ATE, SLT, and HVV teams to establish IDDQ, leakage, and LPM correlations, optimizing the Vmin/Fmax envelope to maximize silicon yield while maintaining aggressive performance tiers.Architectural Trade-off Analysis: Lead deep-dive \"what-if\" PPA analysis to influence CPU configuration, cache hierarchies, and coherent interconnect (NoC) scaling in partnership with PDM and Architecture teams.System-Level Optimization: Oversee workload characterization and system-level tracing on Windows on ARM, Linux, and Android, optimizing DVFS, EAS (Energy Aware Scheduler), and compiler-level interactions.Global Team Leadership: Founded and scaled the BDC CPU Performance organization to 20+ specialized engineers, establishing the technical standards for CPUSS validation across global sites.HVM & SKU Strategy: Advise executive leadership on performance/power risk profiles to define competitive SKU positioning, binning strategies, and OEM launch readiness for 50+ SoCs.Infrastructural Innovation: Architected a remote-access smart lab automation framework for parallel CPUSS experimentation, ensuring zero-downtime delivery of performance sign-offs.

Education

• University of Kerala

  Bachelor of Technology (B.Tech.), Electronics and Communications Engineering

  1996 — 2000

Skills

• Device Drivers
• Rtos
• Unix
• Android
• Embedded Systems
• Software Design
• Linux Kernel
• Linux
• Testing
• Soc
• Digital Signal Processors
• Integration
• Performance Analysis
• Test and Automation
• Benchmarking
• C++
• Shell Scripting
• Software Engineering
• Debugging
• System Architecture
• Agile Methodologies
• Arm
• Operating Systems
• Embedded Linux
• Use Case Analysis
• Software Development
• Scrum
• Algorithms
• System on a Chip (Soc)
• Mobile Devices
• Embedded Software
• Arm Architecture
• C