Shyhpyng Gau
Senior Analog Design Contractor @Amd
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WORK HISTORY
Senior Analog Design Contractor @Amd
Sunnyvale, US
Developed SerDes for HDMI 5.7Gbps Receiver include 2-tape half-rate DFE (decision feedback equalizer) and on chip termination by using TSMC16nm process.
EDUCATION
Nation Tsing Hua University, Taiwan
Bachelor's Degree
SUNY at Buffalo
Master's Degree
ABOUT SHYHPYNG GAU
Over fifteen (15+) years experience in transistor level analog/mixed-signal/RFIC circuit design. Proficient knowledge of PLL for LC tank and ring oscillator type VCO, RF transceiver circuits (mixer, VCO, in-chip Pre-PA driver, VGA), high-speed link transceiver PHY, clock data recovery (CDR) and DLL, regulator, reference circuit, and OpAmps. Built behavior models using Verilog and MATLAB. Intelligent, honest team player, quick learner and adaptable to ongoing challenges.
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