Shyam Rathod
ASIC Physical Design Engineer II at Intel Corporation
- Role
- Asic Physical Design Engineer - Ii at Intel
- Location
- Bengaluru, KA, IN
- LinkedIn followers
- 500 followers
EngineeringView LinkedIn profile
Experience
Asic Physical Design Engineer - Ii
Jun 2014 — Present · IN
Education
Visvesvaraya Technological University
Bachelor’s Degree
2011 — 2014
Skills
- Very-Large-Scale Integration (Vlsi)
- Sdlc
- Root Cause Analysis
- Logic Design
- Windows
- Hp Qtp
- Agile Methodologies
- System Testing
- System Integration Testing
- Prime Time - Sta
- Logic Analyzer
- Test Automation
- Vb Scripts
- Routing Protocols
- Test Planning
- Application-Specific Integrated Circuits (Asic)
- Physical Verification
- Html
- User Acceptance Testing
- Digital Circuit Design
- Jira
- Physical Design
- Placements
- Test Driven Development
- Verilog
- Software Quality Assurance
- Clock Tree Synthesis
- Software Development
- Test Cases
- Functional Testing
- Embedded Systems
- Debugging
- Hp Quality Center
- Logic Synthesis
- Requirements Analysis
- Regression Testing
- Static Timing Analysis
- Digital Electronics
- Ic Complier 2 Synopsys
- Unix
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