Shyam Nair

About Shyam Nair

Silicon Design Engineer with 7+ years of experience specializing in high-performance Static Timing Analysis (STA) and complex Constraint (SDC) management. My core expertise lies in driving timing convergence for large-scale IP and Tile-level designs from RTL to Sign-off.I Architect the infrastructure that makes them faster and more reliable, proven track record of building robust STA methodology frameworks and developing custom automation (Tcl/Bash) that drastically reduces Turnaround Time (TAT) and optimizes PPA (Power, Performance, Area) for critical design partitions.Technical Focus:SDC & Constraints: Expert in building timing constraints from scratch, handling multi-voltage domains, and managing complex clocking architectures.STA & Sign-off: Specialized in Prime-Time and Star-RCXT for deep sub-micron nodes (TSMC, GF, UMC).Automation: Developed the CCX framework—a custom automation layer for timing runs, featuring auto-launch, smart monitoring, and automated documentation.Physical Implementation: Deep experience in PNR (Innovus, ICC2, Fusion Compiler) and Physical Verification (DRC/LVS) using Calibre.

Experience

1. Mts Silicon Design Engineer

   AMD

   Jul 2025 — Present · Bengaluru, IN

Education

• Shri Guru Independent PU college

  Pre University, PCMB

  2010 — 2012

• J S S Academy of Technical Education, BANGALORE

  BE - Bachelor of Engineering, Electronics and Communications Engineering

  2012 — 2016