Shweta Sarap

About Shweta Sarap

I have joined Intel as Formal Verification Intern and currently pursuing my M.S. in Electrical Engineering at Arizona State University, with a passion for digital design, formal verification, and building robust hardware systems.I bring a strong debugging mindset and systems thinking approach to my current focus in hardware. I\'ve been actively working with Verilog and SystemVerilog for both RTL and formal testbench development, and have hands-on experience writing SystemVerilog Assertions (SVA). Skills:• Tools: Jasper Gold FPV, Coverage App, Super lint, Model Sim, JIRA, GIT, JENKINS • Programming Languages: Verilog, System Verilog, Python, Java, C++, System Verilog Assertions, TCL, Shell • Testing Techniques: Functional, Regression tests, Defect Management, Bug Tracking & Fix, Root Cause Analysis

Experience

1. Formal Verification Intern

   Intel

   Jan 2026 — Present · Santa Clara, CA, US

   Architected and Benchmarked Multi-Methodology Scoreboards: Implemented and validated three distinct data integrity verification architectures - Pulse, Wolper, and Double Symbol (SymX/SymY) to evaluate proof convergence and bug-finding efficacy. • Optimized Data Integrity Flows: Determined the optimal break-even points for SymX/SymY versus traditional symbolic indexing, providing a data-driven guide for selecting verification techniques based on design complexity. • Implementing Jasper scoreboard logic for different Chunk sizes handling with parameterization. • Executing Super lint static analysis on HIOP block. • Initiated microarchitectural study of HIOP block for comprehensive Test Planning; Verifying HIOP design features.

Education

• Arizona State University

  Master's degree, Electrical Engineering

• All India Shri Shivaji Memorial Society

  B.E, Computer Engineering

• Modern College of Arts, Science and Commerce

  11 th & 12 th Std, Computer Science

• Department of Technology, Savitribai Phule Pune University

  Master of Technology - MTech, Computer & Information Technology