Shweta Panwalkar

About Shweta Panwalkar

Sr. CAD Lead (Signoff/Timing Methodology), NVIDIA IndiaSr. CAD and Methodology Manager, Marvell IndiaManaging a STA and ECO domain with a team responsible for deploying the central CAD flow for all the Project Teams. Working on technology signoff guidelines (delay margins, constraint margins) to define a robust signoff mechanism. ECO methodologies with tweaker, TSO to achieve faster convergence along with hierarchical design handling. Studying new methodologies like MIS (multi-inputs switching), Interconnect margining, IR aware STA with EDA tool capabilities and deploying through CAD flows for bigger design community.Sr. SoC Design Lead, Intel Bangalore ASIC and Front End Design Manager, Intel BangaloreManaging a team which develops, tests and delivers front end collaterals for AMS IPs, including RTL, ATPG, LIBS, CTL etc. Team also delivers the full ASIC implementation of digital blocks of AMS IPs. ASIC Design Engineer, Intel BangaloreDesign, deploy and support Logic Synthesis, Placement, Routing and Timing for Analog and Mixed signal IP. Post-Silicon bench testing for the IP designed by AMS team, involves parametric, functional and Scan testing with respect to PVT variations with characterization.DA- Timing STA Intel, BangaloreDesign, develop, deploy and support Static Timing Analysis and ECO flowsProduct Development Engineer, Intel OregonResponsible in delivering a robust test infrastructure using ATE. Working in different phases of the product development cycle (design and production) to drive the testability and manufacturability of productsMaster Thesis on:Low noise Injection Locked Ring Oscillator (ILRO) for Clock and Data RecoveryAdviser: Dr. Shahab ArdalanSpecialties: Mixed Signal Designing and Testing

Experience

1. Sr Cad and Methodology Lead (Signoff Timing Methodology)

   NVIDIA

   May 2024 — Present · Bengaluru, IN

   Signoff/Timing Methodology; Silicon Correlation and Timing Estimation; Robust Signoff flows; Tool Qual and regressions

Education

• Shreemati Nathibai Damodar Thackersey Women's University

  Diploma, Electronics

  2004 — 2007

• San José State University

  MSEE, Mixed Signal Design and Testing

  2010 — 2012

• Vivekanad Education Society's Institute of Technology (VESIT)

  BE, Electronics and Telecommuncation

  2007 — 2010

Skills

• Schematic Capture
• Icc
• Primetime
• Edi
• Orcad Capture
• Synopsys Icc
• Tcl-Tk
• Autocad
• Asic
• Cadence Virtuoso
• System Verilog
• Systemverilog
• Tempus
• Tcl
• Analog
• Designer Compiler
• Ovm
• Avm
• Windows
• Orcad
• Testing
• C++
• Veritas Cluster Server
• Verdi
• Ms Office Suite
• Siliconsmart
• Perl
• Vlsi
• Innovus
• Vhdl
• Simulations
• Dreamweaver
• Unix
• Verilog
• Matlab
• Vcs
• Synopsys Primetime
• Modelsim
• Totem
• C