Shuvam Biswas
Sr ASIC Design and Verification Eng @ Synopsys || M.Tech - IIT INDORE | RTL Design and Verification | Intermediate in Verilog SV UVM Python TCL
- Role
- Sr Asic Design and Verification Engineer at Synopsys Inc
- Location
- Kolkata, WB, IN
- LinkedIn followers
- 500 followers
About Shuvam Biswas
I am a passionate engineer with expertise in digital IC design, hardware description languages (Verilog and SystemVerilog), and UVM verification methodologies. My project portfolio includes successful designs and verifications of complex systems like APB, SPI, UART protocols, and synchronous FIFO memory. Additionally, I have designed a RISC microprocessor (MIPS) supporting essential instructions like add, addi, sub, lw, sw, beq, and jump. Proficient in Xilinx Vivado, I hold an M.Tech degree from IIT Indore and a B.Tech degree from RCC Institute of Information Technology.
Experience
Sr Asic Design and Verification Engineer
Dec 2024 — Present · Noida, IN
Education
Indian Institute of Technology, Indore
Master of Technology - MTech, VLSI DESIGN AND NANOELECTRONIS
RCC Institute of Information Technology
Bachelor of Technology - BTech, Electrical, Electronics and Communications Engineering
2017 — 2021
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