Shubham Choubey

About Shubham Choubey

I’m M.Tech graduate from MNNIT Allahabad, currently working as an ATE Test Engineering Intern at Infineon Technologies, with hands-on experience in validation of analog/mixed-signal IPs on the Advantest platform. I’ve worked on multiple USB PD and Hub Controller SoC projects: HX2G3 (USB Hub Controller SOC – NPI) PMG1-B2 (USB PD SOC – NPI) CCG7SAF (USB PD SOC – Sustaining) I developed and validated test programs for Leakage, Bandgap, LDO, POR, and IMO blocks, implemented internal trimming, and brought up the tests on silicon. For CCG7SAF, I did PCR a pre production test program release activity where I verified existing test method logic to reduce test time and increase coverage while ensuring functional compatibility. As part of pre-silicon activity, I performed DIDO replay, converting test vectors into ATE-compatible formats and validating them on the design verification testbench before first silicon bring-up. To accelerate debug, I built a Python-based automation script using Infineon’s internal GPT tool, analyzing 300+ DIDO logs to automate Pass/Fail detection and trace I/O failures to test conditions. I\'m efficient in using AI tools to reduce manual debug and reporting efforts, significantly improving engineering productivity. My M.Tech thesis focuses on DSP-based ATE cost modeling, where I built a MATLAB-based framework using Monte Carlo methods to compare test cost and throughput across DSP and Non-DSP platforms. Coursework includes Digital IC Design, DSP & Advanced DSP, DSP Processor, Advanced Computer Architecture, and Digital Image Processing. Through DSP Processor course I gained detailed understanding of ADC/DAC systems, strengthening my mixed-signal fundamentals. To build design expertise, I completed a national workshop at IIT Indore on schematic-to-layout design using Virtuoso, Calibre, and Synopsys ICC, covering custom layout and backend flow. I’m also enrolled in a 135-hour design program at IIT Kharagpur, focused on analog and digital SoC design using LTspice, Verilog, and Cadence, including blocks like OPAMPs, LDOs, SerDes, and ARM SoC. I aim to combine my test engineering experience with growing design knowledge to contribute effectively to analog/mixed-signal validation and IP-level development.

Experience

1. Intern

   Infineon Technologies

   Jul 2024 — Present · Bengaluru, IN

   Project 1: HX2G3 (USB Hub Controller – NPI Project)Performed DIDO replay to convert test vectors into ATE format and validate them on the design verification testbench.Reviewed board schematics to check which channels can be ganged as per system specs.Reviewed the Bill of Materials (BOM) for all package variants.Brought up the continuity test program for a 48-Lga package wafer sort on ATE.Performed Power-On Reset (POR) testing for analog circuit startup validation.Project 2: PMG1-B2 (Power Delivery – NPI Project)Did Magnum to conversion for CCG4 die (part of dual-die project with TLD5190).Created ATE test program for Internal Main Oscillator (IMO) block.Implemented internal trimming procedure for IMO.Developed test methods for Bandgap block testing and added trimming logic to handle PVT variations using existing design behavior.Brought up continuity test and validated scan patterns for the die.Project 3: CCG7SAF (Sustaining Project)Verified and validated new test method logic on to reduce test time and improve coverage.Ensured test stability and repeatability under production conditions.Additional Contribution: Debug Automation & AI Tool UtilizationDeveloped a Python-based script using Infineon\'s internal GPT tool to analyze and summarize ~300 DIDO vector logs, identifying Pass/Fail status, failing I/O transactions (e.g, IOR, IOW), and mapping issues to corresponding ATE test files, transactions, and test factors.Significantly improved debug speed and traceability by automating the correlation of failures with relevant basic test conditions, eliminating manual review effort.Demonstrated strong efficiency in using Infineon\'s internal AI tools, reducing the time taken for documentation, file generation, and report creation, which were otherwise time-consuming if done manually.Proven ability to apply AI-assisted workflows within ATE test engineering processes, showing adaptability to modern validation environments.

Education

• Bansal Institute of Science & Technology, Raisen Road, Kokta, Anand Nagar, Bhopal - 462021

  Bachelor of Engineering (B.E.)

• Indian Institute of Technology, Kharagpur

  Project-Based VLSI Training Program (Non-Degree)

  2025 — 2025

• Motilal Nehru National Institute Of Technology

  Master of Technology - MTech