Shubham Bhaskarwar
Lead Design Engineer @ Cadence | Master\'s in Electronic Design
- Role
- Lead Design Engineer at Cadence
- Location
- Bengaluru, IN
- LinkedIn followers
- 500 followers
About Shubham Bhaskarwar
Validation Engineer | PCIe Expert | FPGA Prototyping Enthusiast With 6+ years of hands-on experience in PCIe IP validation, I specialize in ensuring high-performance, reliable, and future-ready interconnect solutions. Currently driving PCIe 6.0 Subsystem Validation in Silicon, I bring a strong focus on innovation, precision, and quality. Expertise Highlights-PCIe Protocol (Gen3/4/5/6) – Deep understanding of compliance, validation & interoperability -FPGA-Based Prototyping – Architecting and designing high-speed platforms for IP subsystem validation and demos -System-Level Validation – Hardware bring-up, test automation, and performance analysis Passionate about building cutting-edge solutions, I thrive at the intersection of hardware design, protocol validation, and FPGA systems to enable next-gen connectivity. Let’s connect if you are working on PCIe, FPGA prototyping, or high-speed interface design!
Experience
Lead Design Engineer
Jul 2023 — Present · Bengaluru, IN
Education
Yeshwant Mahavidyalaya, Nanded
HSC
2010 — 2012
Shri Guru Gobind Singhji Institute of Engineering and Technology, Vishnupuri, Nanded
Bachelor of Technology (BTech)
2012 — 2016
Matoshri Vidyalay Mahagaon
SSC
2008 — 2010
National Institute of Technology Calicut
Master's degree
2017 — 2019
Skills
- Vhdl
- Pspice
- Programming
- Java
- C
- Embedded Systems
- C++
- Electronics
- Matlab
- Verilog
- Labview
- Microcontrollers
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