Shruti Vyas
Sr IP Design Verification Engineer at Microsoft
- Role
- Senior Ip Verification Engineer at Microsoft
- Location
- Bengaluru, KA, IN
- LinkedIn followers
- 500 followers
About Shruti Vyas
Experienced Component Design Engineer with a demonstrated history of working in the semiconductors industry. Strong engineering professional skilled in SystemVerilog, Application-Specific Integrated Circuits (ASIC), Perl, Design Rule Checking (DRC), and Integrated Circuit Design.
Experience
Senior Ip Verification Engineer
Mar 2025 — Present · Bengaluru, IN
Education
Birla Institute of Technology and Science, Pilani
Master's degree, Economics
University of Massachusetts Amherst
MS, Electrical and Computer Engineering
2008 — 2010
Birla Institute of Technology and Science, Pilani
Bachelor of Engineering (B.E.), electrical and electronics engineering
2002 — 2007
Birla Institute of Technology and Science, Pilani
Bachelor's degree, Electrical and Electronics Engineering
Skills
- Integrated Circuit Design
- Logic Synthesis
- Systemverilog
- Vlsi
- Vhdl
- Dft
- C++
- Application-Specific Integrated Circuits (Asic)
- Rtl Design
- Perl
- Drc
- Pre-Silicon Validation
- Verilog
- Fpga
- Asic
- Very-Large-Scale Integration (Vlsi)
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