Shriram Vijayakumar

About Shriram Vijayakumar

Scan insertion, verification and post-silicon validation of a multi-million flop count design for the consumer electronics market* Exposure to all aspects of test like Scan/LBIST/MBIST * Successful silicon validation and feature bringup of ATPG and LBIST structures.* Verification and post-silicon validation of all memory BIST systems across GPU/MCP product families* BIST systems for single/dual/multi ported SRAM arrays, latch-based arrays and redundancy systems for arrays* Post silicon validation and bringup of Memory BIST/BISR features on multiple product nodes from 90nm to 40nm.* Yield Analysis/Yield Improvement activities for multiple product lines.* Scan methodology for testing latch array systems.* Silicon validation of scan based Design For Debug features.* Experience developing and maintaining CAD flow methodologies for DFx - Bist Insertion, Failure Analysis, Yield Analysis, TTRSpecialties: Post-Silicon Validation for DFT, Memory BIST/BISR, CAD Flow Development, Scan Planning, ATPG, LBIST

Experience

1. Sr Dft Engineer

   Apple

   Sep 2013 — Present

Education

• PSG College of Technology

  BE, Electronics and Communication

  2000 — 2004

• University of Wisconsin-Madison

  Master of Science (MS), Electrical and Electronics Engineering

  2005 — 2007

Skills

• Tetramax
• Soc
• Logic Design
• Jtag
• Timing Closure
• Asic
• Bist
• Verilog
• Dft
• Test Engineering
• Vlsi
• Atpg
• Rtl Design