Shrinidhi Amble

About Shrinidhi Amble

With a background rooted in semiconductor design, I am deeply immersed in the realm of cutting-edge technologies, specializing in Physical Design (PD) activities that span a range of critical processes. From crafting intricate floor plans to generating abstract views, and from RC extraction to Place and Route (PNR), I am well-versed in the intricacies of chip design methodologies.My expertise extends to encompass Static Timing Analysis (STA), Electromigration (EM), IR Drop analysis, and navigating Design Rule Checks (DRCs) with precision. Moreover, I excel in the crucial task of schematic to layout verification, ensuring the integrity and functionality of designs at every stage.Collaboration lies at the heart of my approach, as I have consistently worked hand in hand with diverse design teams to tackle complex challenges head-on. Whether it\'s addressing design constraints or optimizing performance, I thrive in environments where collective expertise is harnessed for innovative solutions.A significant aspect of my role involves mentoring and supporting team members, offering guidance and assistance in debugging both tool and design-related issues. Through this collaborative spirit, I foster an environment of continuous learning and growth, where challenges are viewed as opportunities for development.My technological journey has seen me navigate the intricacies of semiconductor processes across multiple nodes, including Intel\'s 10 nm and TSMC\'s 5 nm. This breadth of experience has endowed me with a nuanced understanding of the nuances and intricacies inherent in each fabrication process, enabling me to adapt and innovate effectively.Looking ahead, I am driven by a relentless pursuit of excellence in semiconductor design, fueled by a passion for pushing the boundaries of technology. I am eager to apply my expertise and collaborative mindset in dynamic environments, where innovation thrives, and challenges serve as catalysts for growth.

Experience

1. Asic Physical Design Engineer

   Capgemini Engineering

   Mar 2022 — Present · Bengaluru, IN

   Successfully Designed a channel partition in Intel\'s 10nm Technology resulting a Successful Tapeout, developing skills such as Floor Planning, CTS Cells Bounding, Sign-Off STA, DRC clean up, Timing-ECO rollup, while also working with CTS mentors to achieve good skew and latency - Worked on TSMC\'s 5nm block-level design IP for a pivotal partition. Proficiently conducted Static Timing Analysis and managed the Place and Route (PNR) flow- Strategically devised an efficient floorplan for a predominantly macro driven design. Iteratively optimized the layout to alleviate congestion. Implemented precise macro grouping techniques to mitigate timing violations.

Education

• Jyothy Institute of Technology

  Bachelor of Engineering - BE, Electrical, Electronics and Communications Engineering