Shrikant Saxena
- Role
- Location
- San Diego, CA, US
- LinkedIn followers
- 500 followers
About Shrikant Saxena
Experience in pre-silicon verification with expertise in IP/CPU (ARM based) Subsystem…
Experience
Present
Skills
- Rtl Design
- Cmos
- Digital Circuit Design
- Uvm
- Low Power Verification
- System Verilog Assertion
- Uvm Factory Configuration
- Xilinx Ise
- Uvm Tlm-1 Tlm-2 and Configuration
- Modelsim
- I2c Protocol
- Verilog
- Tcl-Tk
- Gate Level Simulation
- Linux (Shell Scripting)
- Fpga Design Flow
- Functional Coverage (System Verilog)
- Systemverilog
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