Shreyas Sudarshan

About Shreyas Sudarshan

I’m a passionate and results-driven Senior PCB Design Engineer with over 6 + years of experience in high-speed, high-density, and mixed-signal PCB designs across consumer electronics, RF, computing hardware, and power systems. End-to-End PCB ExpertiseFrom schematic capture to production-ready Gerbers, I specialize in multi-layer (up to 24 layers) and HDI PCB design using blind/buried vias and microvias, ensuring compliance with IPC Class standards. I integrate SI/PI analysis, EMC guidelines, and DFM/DFT practices for efficient and reliable outcomes. High-Speed DesignI’ve designed boards for DDR3/DDR4, PCIe, USB, and Ethernet protocols with expertise in impedance control, length matching, and differential pair tuning. Skilled in collaborating with SI teams for GHz-level trace simulation and layout optimization — often in tight form-factor constraints with FPGA and SoC integrations. Mixed-Signal SystemsAdept at analog/digital/RF partitioning, I’ve worked on boards combining ADC/DACs, RF front-ends, and analog circuits — managing crosstalk, grounding, and filtering strategies to ensure precision and stability. Power Board DesignExperienced in designing buck, boost, buck-boost regulators, LDOs, and isolated power domains with a strong focus on ripple suppression, thermal management, and creepage/clearance compliance per & IPC-9592. Tools & MethodologiesCAD Tools: Cadence Allegro, Altium Designer, Mentor Xpedition, OrCADSimulation: HyperLynx, LTspice, PI/SI modelingWorkflows: DRC/DFM/DFT checks, BOM optimization, version control, design reviews🤝 Collaboration & ExecutionI thrive in cross-functional teams, working closely with hardware, firmware, mechanical, and manufacturing engineers. Whether it\'s achieving first-pass success or tackling a complex board challenge, I bring precision, collaboration, and innovation to every project.

Experience

1. Pcb Layout Design Engineer

   Capgemini Engineering

   Apr 2024 — Present · Bengaluru, IN

   Designed compact HDI boards with blind/buried vias and microvias for BGA packages in tight layouts.>Routed high-speed signals for FPGA, RF, and SoC systems following DRC/DFM and IPC Class standards.>Reduced board area by 30% through optimized placement and via strategy without compromising EMI or thermal performance.>Collaborated on SI constraints, including differential pair tuning and length matching for DDR, PCIe, and USB.>Developed power supply boards with LDOs, switching regulators, and isolation techniques per DFM/DFT reviews, vendor communication, and ensured manufacturability.

Education

• Dept of Technical Education

  Diploma, Electrical and Electronics Engineering

• Bangalore University

  Bachelor of computers -BCA