Shreyas Puttanna
Signal Integrity Engineer at Cisco
- Role
- Signal Integrity Engineer at Cisco
- Location
- Bengaluru, KA, IN
- LinkedIn followers
- 500 followers
About Shreyas Puttanna
Signal integrity Design - Stackup design, connector selection, PCB routing layers optimization, defining PCB design rules, reviewing designs in Allegro, strong understanding of PCB design constraints and DFM constraints.Simulation - Ansys HFSS 3D simulation upto 224Gbps, keysight ADS, COM simulations, connector and BGA footprint impedance & crosstalk optimization, BGA PKG-PCB co-simulationPower integrityPCB PDN impedance simulation in cadence PowerSI & OptimizePI, Loop inductance optimization, Decap values optimization.Measurements - Frequency domain measurements in VNA, Spectrum analyzer & phase noise analyzer.Time domain measurement in Real-time oscilloscope, Sampling-time oscilloscope, BERT & TDR. TP1A and TP4 compliance measurements.SerDes characterization, SerDes equalization tuning & System level SI Failure analysis.Python - Data analysis and visualization using pandas and matplotlib. Instrument automation.
Experience
Signal Integrity Engineer
Mar 2022 — Present · Bengaluru, IN
Education
RR Institute Of Technology
Bachelor of Engineering (B.E.)
2010 — 2014
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