Shreyas Joshi

About Shreyas Joshi

I hold a Master\'s degree in Electrical Engineering from Boston University with a specialization in Digital and Analog VLSI, post which I have been working as a VLSI Design engineer since 2019.As an FPGA Design Engineer at Microchip, I have exposure to various stages of ASIC design flow, with a focus on RTL design of PCIe and USB protocols for Physical Interface for PCI Express (PIPE). I have a deep understanding of both the PHY and MAC layers (LTSSM). Beyond RTL design, I have experience with signoff flows such as CDC and Lint and have also worked on interface level STA.During my Master\'s, I gained a strong academic and practical knowledge of Computer Architecture, and have a strong interest in processor design, cache memory design and related topics. I also gained extensive knowledge in the subject of Analog/RF IC design, in which, I studied and designed a variety of circuits such as Op-Amps, ADC/DAC, LNA, VCO, PLL.

Experience

1. Senior Design Engineer - 1

   Microchip Technology Inc.

   Jul 2021 — Present · Hyderabad, IN

   RTL design engineer on PHY Layer- Design of PCIe protocol (Gen1-Gen5) in Physical Interface of PCI Express (PIPE)- PCIe Gen1-5 LTSSM (MAC layer)- Unit level testing for PCIe PIPE features- Debugging and waveform analysis using QuestaSim and Questa Visualizer- Signoff flows such as CDC, lint using Synopsys VC-Spyglass and interface level STA

Education

• Fr Conceicao Rodrigues College of Engineering Band Stand Bandra (West) Mumbai 400 050

  Bachelor of Engineering (B.E.), Electrical and Electronics Engineering

  2011 — 2015

• Boston University College of Engineering

  Master of Science (MS), Electrical and Electronics Engineering

  2016 — 2018