Shreyansh Agrawal
Senior Design Verification Engineer @ Analog Devices| SoC Verification
- Role
- Senior Design Verification Engineer at Analog Devices
- Location
- Bengaluru, KA, IN
- LinkedIn followers
- 500 followers
EngineeringView LinkedIn profile
About Shreyansh Agrawal
Interested in VLSI Design/Formal Verification using FPV. Have a fair bit of experience in…
Experience
Senior Design Verification Engineer
Mar 2024 — Present
Education
National Institute of Technology Kurukshetra
Master of Technology - MTech, vlsi design
2019 — 2021
Gyan Ganga Institute of Technology Sciences
Bachelor of Engineering - BE, Electrical, Electronics and Communications Engineering
2014 — 2018
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