Shreedhar Edar
Experienced Memory Layout Design Engineer | Expert in TSMC FinFET 7nm, 5nm, and 3nm Technologies | Skilled in SRAM Compiler Development | Proficient in Memory Optimization Techniques
- Role
- Memory Layout Design Engineer at Texas Instruments
- Location
- Bengaluru, IN
- LinkedIn followers
- 500 followers
EngineeringView LinkedIn profile
Experience
Memory Layout Design Engineer
Feb 2023 — Present · Bengaluru, IN
Education
S T J Institute of Technology, RANEBENNUR
Bachelor of Engineering - BE
2013 — 2017
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