Shrayansh Gupta

About Shrayansh Gupta

Greetings! I\'m Shrayansh Gupta, a dynamic VLSI Engineer currently making strides as a Design Engineer at Tessolve. In this exciting role, I\'m dedicated to serving the esteemed client, Texas Instruments, as a PCELL Designer. In my ongoing journey in the world of VLSI, I bring a wealth of experience from my role as a Member of Technical Staff at HCL Technology(Client-INTEL), specializing in PDK Frontend Verification for advanced technology nodes like 7nm, 10nm, 16nm, and 22nm. My forte includes a spectrum of skills, from creating intricate testbenches and collaborating with Backend Teams for layout generation to mastering pre-layout and post-layout simulations, statistical design methodology, and reliability analysis. My diverse skill set spans Schematic and Layout Design, scripting in Shell, BASH, Perl, and Python, ASIC Design Flow, Verilog, and proficiency in EDA tools such as Cadence, Synopsys, Siemens, and Xilinx. In addition to my technical prowess, I recently embraced a new challenge as a Design Engineer at Tessolve. Here, I focus on crafting innovative solutions as a PCELL Designer for Texas Instruments, leveraging extensive knowledge of CADENCE SKILL programming language and the Open PCELL DESIGNER TOOL. Beyond the technical, I bring a collaborative spirit, a penchant for innovation, and an eagerness to learn. In a world that constantly evolves, I am committed to staying at the forefront of VLSI technology, contributing my skills to projects that redefine the industry. Let\'s connect and explore the possibilities at the intersection of technology and innovation!

Experience

1. Design Engineer

   Cadence

   May 2024 — Present · Bangalore Urban, IN

   Working as an PDK/QA flow developer and Creating supporting PCells for Design.

Education

• Raj Kumar Goel Institute of Technology, Ghaziabad

  B.Tech, Electronics and Communications Engineering

  2017 — 2021