Shravani Rompally
Design Verification Engineer i @Hysoc Technologies Pvt Ltd
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WORK HISTORY
Design Verification Engineer i @Hysoc Technologies Pvt Ltd
Hyderabad, IN
EDUCATION
Joginpally B.R Engineering College
Bachelor of Technology - BTech, Electrical, Electronics and Communications Engineering
Siddhartha Junior College
Intermediate, Maths Physics and Chemistry (MPC)
ABOUT SHRAVANI ROMPALLY
A competent and enthusiastic engineer who is passionate about learning new things constantly and connecting with like-minded people in the industry- Adept in HDL/HVL languages like Verilog, System Verilog- Highly competent in Methodologies like UVM, Coverage Driven Verification and Assertion Based Verification- Have exposure to various tools like VCS-Synopsys, Riviera Pro – Aldec, ISE-Xilinx, Verdi-Synopsys- Extensive knowledge of universal protocols like APB, AXI, SPI.
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