Shraddha P.

About Shraddha P.

Hello, I graduated from the University of Southern California in 2017 with MS in Electrical Engineering. Currently, I am working as a Design Verification Engineer in the Mini -SOC team at SARC, Austin. To share any job opportunities or network around, please send an inmail. Area of Interest: Design Verification,2.Programming Languages:Knowledge of Verilog, System Verilog, Perl, Python, C++, UVM experience3.Worked on Semiconductor Design Tools: Simulations on Modelsim and QuestaSim, FPGA (Xilinx ISE and Altera Quartus), Cadence-Virtuoso, NCVerilog, Synopsys DC, Synopsys -PrimeTIme, Cadence. Believes in Teamwork has good communication skills and has enthusiasm for the right time approach.

Experience

1. Senior Design Verification Engineer

   Qualcomm

   Sep 2020 — Present

Education

• University of Southern California

  Master’s Degree, VLSI and Computer Architecture

  2015 — 2017

• SYMBIOSIS INTERNATIONAL UNIVERSITY

  Bachelor’s Degree, Electronics and Communications Engineering

  2011 — 2015

Skills

• Perl
• Leadership
• Application-Specific Integrated Circuits (Asic)
• Cgi/Perl
• Java
• Universal Verification Methodology (Uvm)
• Digital Electronics
• Painting
• Debugging
• Systemverilog
• Public Speaking
• Verdi
• Field Programmable Gate Arrays (Fpga)
• Rtl Design
• Simulations
• Functional Verification
• Microsoft Excel
• Powerpoint
• Xilinx Ise
• Python
• Research
• Verilog
• Windows
• Field-Programmable Gate Arrays (Fpga)
• C++
• Microsoft Word
• Matlab
• Modelsim
• Computer Architecture
• Customer Service
• Autocad
• C
• Programming
• Microsoft Office
• Rtl Verification
• Cadence Virtuoso
• Teamwork