Shivansh Pandey

WORK HISTORY

EDUCATION

ABOUT SHIVANSH PANDEY

I’m an M.Tech candidate in VLSI Design at IIT Mandi with a deep interest in the end-to-end digital design flow — from RTL development to timing, testability, and silicon validation. Currently, I’m a Post-Silicon Validation Intern at Infineon Technologies, where I work on validating SoC designs and ensuring functional accuracy and performance in real hardware environments.My expertise includes RTL design using Verilog, Static Timing Analysis (STA), Design for Testability (DFT), and an understanding of Physical Design (PD) concepts like clock tree synthesis and power optimization. This multidisciplinary exposure allows me to view chip design holistically — ensuring that logic, timing, test, and layout integrate seamlessly into a manufacturable, high-yield silicon.I enjoy solving design bottlenecks that demand both analytical and creative thinking — whether it’s debugging timing violations, optimizing logic for area and power, or validating post-silicon behavior. My approach combines technical precision with curiosity and collaboration, aiming to bridge academic rigor with real-world semiconductor challenges.I’m now seeking opportunities in Digital Design, STA, DFT, or Physical Design engineering, where I can contribute to the creation of efficient, reliable, and innovative semiconductor solutions.If your team is building the next generation of digital systems, I’d love to connect and explore how I can add value to your design and verification efforts.