Shivani Rajmane
RTL Design & Verification intern @ Maven Silicon | ASIC Design professional | Master\'s in VLSI @ VIT | Physical Design Enthusiast | Synopsys Verdi |
- Role
- Maven Silicon
- Location
- Sangli, MH, IN
- LinkedIn followers
- 500 followers
About Shivani Rajmane
A passionate Electronics and Telecommunication who have a true interest in VLSI…
Experience
Present
Education
DKTE'S Textile and Engineering Institute - An Autonomous Institute
Bachelor's degree
2019 — 2023
Vellore Institute of Technology (VIT)
M.TECH
2024 — 2026
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