Shivani Yadav

About Shivani Yadav

Western Digital benefits from over nine years of experience in ASIC and SoC design verification. As a Principal Engineer, my focus is on delivering advanced storage solutions in the Enterprise Flash and HDD domains. My work involves driving complex verification efforts, including emulation projects and FPGA prototyping, as well as architecting testbenches using SystemVerilog and UVM. I contribute to ensuring robust verification of high-speed protocols such as PCIE, NVME, and ARM Processor. In my role, I oversee team deliverables, mentor engineers, and implement scalable verification strategies under tight deadlines. My leadership and people management skills enhance cross-functional collaboration, enabling the achievement of crucial project goals. Through publications and my commitment to the semiconductor industry, I aim to contribute to innovation while advancing technology to support Western Digital\'s mission.

Experience

1. Principal Engineer

   WD

   Jul 2023 — Present · Bangalore Urban, IN

Education

• IIMT engg college

  Bachelor of Technology (BTech), Electronics and Communications Engineering

  2009 — 2013

• Amity University

  Master of Technology (MTech), VLSI

  2013 — 2015

Skills

• Fpga
• Semiconductors
• Debugging
• Asic
• Tcl-Tk
• Cadence Virtuoso
• Altera Quartus
• Modelsim
• Vlsi
• Electronics
• System Verilog
• C
• Programming
• Integrated Circuit Design
• Embedded Systems
• Soc
• Rtl Design
• Xilinx
• Systemverilog
• Silvaco
• Logic Synthesis
• Uvm
• C++
• Verilog
• Xilinx Ise
• Matlab
• Ubuntu
• Vhdl
• Simulations
• Hdl Designer
• Functional Verification