Shivani Garg

About Shivani Garg

SoC STA Design Engineer>Owned internal/interface timing analysis, ECOs, timing/DRVs closures and sign-off across all modes/corners> Provide RTL and place/opt feedbacks after timing violations, UCR, check_timing, quality analysis internally and at full chip> Constraints development with RTL team for internal and interfaceviolations at every milestone> Quality/Paranoia Checks like gray pointer checks, log reviews, ETM lib QC,clock muxes clocking, unconstrained endpoints> Owned clock definitions/compilation/reviews for partitions/full-chip working with clocking architectASIC synthesis Product Engineer• Currently working as Lead Product Engineer at Cadence Design Systems Pvt. Ltd.• Having 4.5 years’ experience as ASIC Synthesis Product Engineer (functional/customer engagement) in VLSI Industry and Specialization in VLSI design (M.Tech).• Have successfully lead various customer engagements in terms of evaluation, flow development, proliferation, deployment and support.• Have hands-on experience and good understanding of complete Genus/Oasys synthesis tool flows(logical/physical synthesis) and methodologies.

Experience

1. Silicon Design Engineer

   AMD

   Feb 2026 — Present · Bengaluru, IN

   Synthesis and Constraints

Education

• Institute Of Technology And Management

  Master's Degree, VLSI Design

  2013 — 2015

• Maharshi Dayanand University

  Engineer's Degree, Electrical, Electronics and Communications Engineering

  2009 — 2013