Shivang Patel

About Shivang Patel

Quality Engineer & Process Improvement Specialist with 3+ years of experience driving compliance, efficiency, and innovation in regulated industries including manufacturing, RF/SAR testing, and automation. Skilled in Six Sigma, Lean Manufacturing, PFMEA, root cause analysis, and regulatory compliance (ISO 9001, FCC, ISED, FDA 21 CFR). Proven ability to lead cross-functional projects that improve product reliability, reduce cycle time, and enhance test automation using tools like Python, Minitab, and LabVIEW. Experienced in developing SOPs, inspection plans, and validation protocols. Enthusiastic about using data-driven insights and quality engineering principles to improve processes, ensure safety, and deliver consistent, high-performance outcomes.

Experience

1. Mfg Test Engineering

   Quanta Computer Inc. 廣達電腦

   Nov 2025 — Present · Fremont, CA, US

   Executed rack-level functional, pretest, burn-in (RUNIN), and final system testing on Oracle GB200 GPU compute platforms to validate shipment readiness and long-term reliability-Validated end-to-end system stability across compute trays, NVSwitch trays, power shelves, PMCs, cable cartridges, and rack infrastructure in high-density GPU environments-Performed root-cause analysis of complex hardware failures involving GPUs, NVSwitches, NVLink, PCIe, NICs (CX7/CX8), BMC/ILOM, PMCs, and power subsystems-Diagnosed NVSwitch NVOS version mismatches, CLI access failures, and health status errors using ONIE recovery, PXE firmware workflows, and serial console access-Debugged NVLink bandwidth stress failures, BER threshold violations, and connectivity pre-check errors through topology mapping and GPU-to-switch correlation-Investigated PCIe compare failures, GPU enumeration issues, and “fallen off bus” events using Linux logs, kernel diagnostics, and ILOM fault data-Resolved BIOS and SBIOS deadlocks, TPM detection issues, and platform initialization failures impacting system bring-up and test progression-Isolated power-related issues by validating PSU detection, PMC behavior, I2C communication, FRU data integrity, and GPIO sequencing at rack scale-Troubleshot network and cabling issues across fiber, DAC, and RJ45 connections, verifying Arista TOR switch interfaces, link status, and negotiated speeds-Leveraged internal automation tools (jumpin, find_ip, ilom, L15H_UUT_hostup.py) and Linux/Bash scripting to automate diagnostics, power cycling, log collection, and targeted retesting-Analyzed rack-level logs, diagnostic flags, and sensor data to identify failure patterns, perform targeted reruns, minimize downtime, and improve production throughput-Documented debug procedures, corrective actions, and shift handoffs while training new technicians on L11 testing, Linux usage, and structured hardware debug workflows.

Education

• Gujarat Technological University (GTU)

  Bachelor's degree, Electrical Engineering

  2014 — 2018

• California State University - East Bay

  Master's degree, Engineering/Industrial Management