Shiva R.

About Shiva R.

PCIe/NVMe/USB4 Verification Engineer with 5+ years of experience in UVM-based ASIC/SoC verification across high-speed interconnects. I work end-to-end on verification strategy, reusable UVM components, coverage closure, regression stability, and deep protocol debug—partnering closely with RTL, PHY, and firmware teams.• Currently at Synopsys, I verify PCIe Gen5 Controller IP/Sub-systems used in data center, AI accelerator, and networking SoCs—covering LTSSM validation, equalization/recovery flows, power management, error handling, stress DMA, and simulation-to-silicon correlation. Previously at Truechip, I built/verified VIP and environments for NVMe (SQ/CQ, PRP, DMA integrity) and USB4 TMU + PCIe tunneling, including CTS-aligned monitoring and high-speed compliance scenarios.• Core strengths: PCIe Gen3/4/5, NVMe, USB4/USB3/USB2, USB PD/Type-C • SystemVerilog/UVM/SVA • Verdi/SimVision • Python automation • Coverage-driven signoff • Root-cause debugging. Open to: PCIe/NVMe/USB4 verification, VIP development, and high-speed protocol validation roles.

Experience

1. Pcie Verification Engineer

   Synopsys Inc

   Mar 2025 — Present · Portland, OR, US

   Currently, I am driving pre-silicon functional verification for PCIe Gen5 Controller IP and Subsystem solutions targeted at modern data centers, AI accelerators, and networking SoCs. My core focus revolves around UVM-based validation of high-speed links, power management features, and rigorous PCI-SIG compliance coverage. Day-to-day, this involves deep-diving into complex LTSSM state transitions, specifically analyzing and resolving equalization Phase 2/3 failures by tracing preset requests and coefficient updates to identify incorrect mappings at the PHY interface. To bridge the gap between simulation and post-silicon, I actively correlate hardware trace captures with LTSSM logs to isolate elusive link training discrepancies. Beyond direct debug and stress-testing long burst DMA transfers, I have built robust Python automation to streamline regression log parsing and coverage aggregation, ensuring our verification cycles are both stable and efficient. Collaboration is key in this role; I work closely with PHY teams to analyze PIPE interface timing mismatches and participate heavily in compliance review meetings to guarantee robust IP delivery.

Education

• Oregon State University

  Master's degree, Electrical and Electronics Engineering