Shiva Nagendar

About Shiva Nagendar

13+ Years of rich experience in ASIC Front-end Verification.2. Worked on SoC, IP Level and Block level Verification activities.3. Worked on ADAS Products complying ISO 26262 standard w/ ASIL-B 4. Worked on Gate Level Simulations and debugging timing violations.5. Worked on Formal Verification using Cadence IFV / Jasper, VC-Formal, Questa formal tools to check the connectivity of IP’s.6. Developed verification environment components such as reference models, checkers, functional coverage models and assertion monitors.7. Worked on the functional coverage and code coverage.8. Good knowledge of Verilog HDL.9. Good Knowledge of HVL such as System Verilog.10. Worked on verification methodology such as UVM.11. Good knowledge in protocols such as I2C, SPI, SCB, APB, AHB, AHB Lite.12. Good in development of simulation plans at block level and at Subsystem/ Cluster level.13. Knowledge on Metric Driven Verification using eManager14. Good understanding of usage of System Verilog assertions.15. Debugged the errors and failures at all stages of verification.16. Worked on Perl scripts to run the simulations, regressions etc17. Worked on different version control systems such as ClearCase, CVS, SVN, design sync18. Good working knowledge of simulator tools such as Cadence ncsim, VCS, Questasim, Visualizer, Modelsim, simvision, Debussy, nWave.

Experience

1. Senior Staff Engineer Manager

   Qualcomm

   Dec 2025 — Present

Education

• JNTUH College of Engineering Hyderabad

  Bachelor of Technology (B.Tech.), Electronics and Communications Engineering

  2006 — 2010

Skills

• Verilog
• C
• Application-Specific Integrated Circuits (Asic)
• Uvm
• System on a Chip (Soc)
• Gls
• Perl
• Semiconductors
• Formal
• Functional Verification
• Debugging
• Rtl Design
• Linux
• Modelsim
• Fpga
• Asic
• Tcl
• Systemverilog
• Vhdl
• Vlsi
• Soc
• Formal Verification