Shiny Crismitha D Souza
Analog Layout Methodology Intern at Intel technologies | Pursuing Masters in Microelectronics and VLSI technology at MSIS, Manipal
- Role
- Analog Layout Methodology Intern at Intel
- Location
- Mangaluru, KA, IN
- LinkedIn followers
- 500 followers
About Shiny Crismitha D Souza
VLSI Design professional with hands-on experience in analog custom layout, verification…
Experience
Analog Layout Methodology Intern
Jun 2025 — Present · Bengaluru, IN
Education
Manipal School of Information Sciences
ME
Vikas Pre-University College - India
PUC, Science
2018 — 2020
Holy Family School-Bajpe
High School
2015 — 2018
NMAM Institute of Technology
Bachelor of Engineering - BE, Electronics and Communications Engineering
2021 — 2024
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