Shilpa Prakash

About Shilpa Prakash

20+ years of experience in ASIC verification end-to-end flow - from planning -> execution -> tape-out -> post silicon support- Expertise in SoC & IP verification- Expertise in feature extraction, scenario identification & development of verification plan- Expertise in design & development of verification components using System Verilog (SV) & UVM methodology & SVA- Excellent debugging skills with ability to root cause to line of RTL- Coverage modeling & Coverage analysis (Functional/Code/UPF)- Gate Level Simulation (GLS) with SDF- Power Aware Verification using UPF- Protocols: DDR, AMBA (AXI, AHB, APB)- Hardware Descriptive Language (HDL)- System Verilog, Verilog- Hardware Verification Language (HVL)- System Verilog- Simulation & Debugging Tools - Incisive, VCS, Verdi, DVE

Experience

1. Sr Staff Design Verification Engineer

   NVIDIA

   Jan 2026 — Present · San Francisco, CA, US

   Continuing the work of building LPUs at a different scale all together!

Education

• Cochin University of Science and Technology

  Bachelor of Technology (B.Tech.), Electronics and communication

  2002 — 2006

• Indian High School Dubai

  Grades K-12

  1989 — 2002

Skills

• Vlsi
• Amba Ahb
• Specman
• System on a Chip (Soc)
• Systemverilog
• Open Verification Methodology
• Uvm
• Soc
• Application-Specific Integrated Circuits (Asic)
• Modelsim
• Vmm
• Verilog
• Vhdl
• Functional Verification
• Ncsim
• Asic