Shichen Justin Qiao
ASIC Design Engineer @ NVIDIA
- Role
- Asic Design Engineer at NVIDIA
- Location
- Santa Clara, CA, US
- LinkedIn followers
- 500 followers
About Shichen Justin Qiao
Hello, LinkedIn community! My name is Shichen Qiao, and I go by Justin. I am a passionate RTL designer and computer engineer with experience across the hardware, firmware, and software domains.My past research focuses include Hyper-Dimensional Computing (HDC) SoCs for low-power neuro-symbolic learning, performance-accurate simulators for NVIDIA GPUs, and FPGA-based control systems for phased array antennas. I have also led the development of three distinct processors, encompassing the RISC-V ISA, the MIPS ISA, an floating point co-processor, various cache systems, and machine learning accelerators.I hold a Master\'s Degree from UC Berkeley EECS and a Bachelor\'s Degree from UW-Madison ECE.Please check the following sections for more details about my research and projects!
Experience
Asic Design Engineer
Jun 2024 — Present · Santa Clara, CA, US
RTL design, synthesis, and timing closure for memory subsystem digital IPs within state-of-art SoCs
Education
University of Wisconsin-Madison
Bachelor of Science, Computer Engineering, Computer Sciences
Washington University in St. Louis
High School Summer Scholars Program
University of California, Berkeley
Master of Engineering, Electrical Engineering and Computer Science
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