Shew Juan Kok

Asic Design Engineer @Aion Silicon

Theale, GB

Automated front-end design flows using Python, TCL, and Shell scripting, significantly reducing manual effort and improving design cycle efficiency- Led front-end design initiatives using SystemVerilog for complex IP and SoC projects, driving development from architectural specification through to implementation- Established and integrated a company-wide linting methodology using Synopsys VC Spyglass, enhancing code quality and consistency across all design teams- Designed and architected system-level solutions, including the integration of third-party and in-house IP for advanced SoC implementations- Performed early-stage design exploration for critical subsystems using Synopsys RTL-Architect, optimizing for performance and area to \"shift left\" the design process- Executed comprehensive functional verification plans using constrained-random methodologies and assertions to ensure designs met rigorous specification requirements- Managed DFT implementation for large-scale, ASIL-B compliant SoCs, developing and debugging ATPG patterns with Synopsys TestMax to achieve over 90% test coverage- Architecture Design Exploration for advance SoC designs as a case study- Version control management using Git and Subversion (SVN) for better team collaboration.EDA TOOLS:• DFT Tools - Synopsys TestMax for DFT ATPG pattern development and debugging at SoCs level • Front-end Tools - Synopsys Design Compiler, RTL-Architect for synthesis and exploration• Static Formal Tools - Questa Static Formal / VC Spyglass, code quality check and best practices• Verification Tools - Verdi, VCS, coverage analysis tools and waveform analysis