Sherwin Bryan Soans
CPU Design Verification Engineer @ Intel Corporation | MEng in VLSI Design
- Role
- Cpu Design Verification Engineer at Intel
- Location
- Mangaluru, KA, IN
- LinkedIn followers
- 500 followers
About Sherwin Bryan Soans
Experienced in building test infrastructure, implementing constrained random tests, and debugging test failures with waveform analysis and log. Fluent in UVM, SystemVerilog, C++, and scripting languages such as Python. My background involves hardware implementation of a RISC-V processor as well as the development of an AI-driven adaptive headlamp system based on CNNs. I am excited about using technology to tackle complicated problems and am actively expanding my knowledge of neural networks, machine learning, LLMs and VL-JEPA.
Experience
Cpu Design Verification Engineer
Jul 2024 — Present · Bengaluru, IN
Took ownership of features which included checker coding, test case development, and coverage writing. • Worked on constrained random test generation • Implemented Core test environment injection.• Debugged test failures using waveform analysis and log examination to pinpoint discrepancies between the test output and the golden reference model.• Helped new team members with methodology and basic debugging. • Assisted other team members with their coverage hits.
Education
St Joseph Engineering College, Mangaluru
Bachelor of Engineering - BE, Electronics and Communication Engineering
2018 — 2022
St. Aloysius (Deemed to be University)
Physics, Chemistry, Mathematics, Electronics.
Manipal School of Information Sciences
Master of Engineering - MEng, VLSI Design
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