Sherif Elewa

About Sherif Elewa

With a strong foundation in hardware digital design for ASIC and FPGA, I have improved my…

Experience

1. Asic Digital Design R & d Engineer - Graduate Research Assistant

   Electroscience Laboratory

   Sep 2023 — Present · Columbus, OH, US

   Post Quantum Cryptography Processor Hardware Design a. Designed and Implemented Application-Specific Crypto-Processor for FIPS-204 standard operating at 300 MHz with a pipelined Harvard architecture. b. Developed a memory scheduling architecture integrating 3 independent memory banks for optimized data access and parallel processing. c. Designed and Integrated complex cryptographic components, including a Number Theoretic Transform engine and a secure noise generation module for efficient lattice-based cryptographic operations. d. Developed and mathematically optimized an innovative modular reduction technique based on Barrett modular reduction algorithm, enhancing computational efficiency. Designed a novel 12-bit modular arithmetic multiplier using this technique, achieving 15% area reduction and 30% performance improvement over existing designs in the literature.2. Completed ASIC physical design tapeout on 12LP GF technology for a 4mm2 chip designed to support Post-Quantum Cryptography and Fully Homomorphic Encryption. a. Designed and Implemented Number Theoretic Transform engine worked at 312 MHz in Fully Homomorphic Encryption crypto-processor including complex blocks such as modular multiplier, Twiddle factor generator, and data interconnect with SRAMs. b. Verified the design by running post-synthesis and post-physical timing simulations.3. Implemented 8x8 mesh-based embedded FPGA (eFPGA) architecture using OpenFPGA and VPR toolchain. a. Architecture Building Blocks: 512 synchronous fracturable LUT4, local and global switching blocks, and 20 efficient DSP blocks performing modular arithmetic multiplication.4. Developed a fracturable Look-Up-Table (LUT4) cell utilized for DNN applications. a. Accomplishment: offers up to 40% logic utilization improvements for neuromorphic systems.

Education

• Faculty of Engineering at Cairo University

  Bachelor's Degree, Electrical, Electronics and Communications Engineering

  2005 — 2010

• Faculty of Engineering at Cairo University

  Master’s Degree, Computer Hardware Engineering

  2012 — 2017

• The Ohio State University

  Master's degree, Computer Hardware Engineering

• The Ohio State University

  PhD, Computer Hardware Engineering