Patrick Sheridan
TPU Architect
- Role
- Chip Architect at Google
- Location
- Boulder, CO, US
- LinkedIn followers
- 500 followers
About Patrick Sheridan
System architecture engineer with interests at the intersection of AI and hardware. I use HW/SW co-design to guide architecture decisions and modeling to evaluate microarchitectural tradeoffs. I have experience with distributed AI model performance optimization, LLVM, SystemC, Python, gem5, and FPGA prototyping. I have worked with technologies including Google\'s TPUs, CXL, HBM, RRAM, and NAND Flash.
Experience
Chip Architect
Nov 2021 — Present · Boulder, CO, US
Own compute core architecture definition Distributed AI model performance optimization Hardware / software codesign
Education
Virginia Tech
BS, Computer Engineering
2005 — 2009
University of Michigan
Doctor of Philosophy (PhD), Electrical Engineering
2010 — 2015
University of Michigan
Master of Science (MS), Electrical Engineering
2010 — 2012
Virginia Tech
BS, Mathematics
2005 — 2009
Skills
- Hardware Architecture
- Field-Programmable Gate Arrays (Fpga)
- Systemc
- Python
- Latex
- Algorithms
- C++
- Verilog
- Engineering
- System Architecture
- Matlab
- Unix
- Characterization
- Hardware
- Semiconductor Fabrication
- Simulations
- Embedded Systems
- Data Visualization
- Troubleshooting
- C
- Research
- Semiconductors
- System on a Chip (Soc)
- Testing
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