Shekher Janagam

About Shekher Janagam

I possess 3 Years of relevant work experience in analog layout design in advanced CMOS process.• Experienced in designing Analog layouts in the process nodes Intel 7nm and TSMC 7nm and, TSMC 5nm(N5), N2, N3, tsmc28nm and tsmc16nm.• Layout tools: Cadence virtuoso.• Verification tools: Calibre, ICV and Totem (RV verification tool)• Completed training of TSMC 28nm and 16nm.• Skilled in designing layouts which involves, floor plan, signal routing plan, matching, ECOs and PDK changes.• Experienced in LV verification flows involving DRC, LVS, Density, Antenna, PV bundle flows, RV related issues ECO implementations and PDK changes.• Good knowledge in matching and shielding.• Good understanding in Analog Layout fundamentals (e.g. Matching, Electromigration, Latch up, Crosstalk, IR drop, parasitic devices, ESD, Short channel effects, Fabrication process)• I have hands on experience of Critical Analog Layout design of blocks such as PLL, Transmitter, Receiver, CTLE, Differential amplifier, LDO, DDR, SERDES blocks, Current mirrors, BGR,Decoder, Ring oscillator.• Ability to understand design constraints, implement high-quality layouts and deliver them on-time.• Efficient in module layout work involves Area estimation, Floor planning, Define pin locations, LEF, Matching Placements & Routings, Power grid generation, Top-level integration & routings.

Experience

1. Senior Layout Designer

   Mirafra Technologies

   Feb 2025 — Present · Hyderabad, IN

Education

• CVR College of Engineering, Hyderabad

  M.TECH, VLSI

• Brilliant Institute of Engineering and Technology

  b.tech, Electronics and Communications Engineering

• Zp High School Namapuram

  Ssc

• Brilliant Institute of Engineering and Technology

  Diploma of Education, Electronics and Communications Engineering