Sheetal Sutar-Govardhane

About Sheetal Sutar-Govardhane

I am self-motivated and enthusiastic. My good logical capability and passion for digital electronics describe me as a good digital design engineer.

Experience

1. Soc Design Engineer

   Intel

   Apr 2018 — Present

   May 2024-Present: Subsystem design lead owning responsibilities of integrating IPs into subsystem Lint, CDC, logic Synthesis, UPF, FEV, DFT,RDL quality val debug support May 2023- April 2024:Took a year long Maternity leave, explored the unknown dimensions of my personality while growing up as a mom with fantastic rejuvenation!20••••23: Worked as a RTL designer for AI HW acceleration IP and networkingIP : Developed microarchitecture and SV RTL design for AXI compatible load-store module, systolic array, arbiter, performance monitor and event filter. Owned the post silicon validation support for functional safety IP - Received DRA (Division Recognition Award) for one of the debug supports. Automated lint and CDC report summary extraction for easy tracking. Owned Lint and DFD for networking IP. 20••••20: TUV audit documentation owner for Functional Safety SOC. Was part of TUV (Technischer Überwachungsverein - Technical Inspection Association) audit presentation team. Developed a methodology for HW Traceability to ease the Functional Safety Traceability.>The HW traceability work product passed the TUV audit in first presentation itself and no follow-up rounds were needed20••••20: CSR RDL owner of multiple SoCs Handled RDL integration and RDL quality checks Developed a Automation for analyzing quality of RDL – > Work bandwidth reduced by ~80%, time to resultant reduced by ~70%.

Education

• KIT's college of engg,Kolhapur

  Engineer’s Degree

  2010 — 2014

• Vishwakarma Institute Of Technology

  Master of Technology (M.Tech.)

  2015 — 2017