Shastry Ragavendra

About Shastry Ragavendra

Extensive experience in Functional Verification of complex ASICs and SoCs- Experience in Project Planning, Project and Team management- Experience in Video; Networking and Storage Domains- Expert in Specman, System Verilog, Verilog HDL- Worked on VMM, UVM and eRM methodologies- Protocol knowledge : VBUSP, OCP, AXI, AHB, OTN, PCIe

Experience

1. Eng Manager

   Intel

   Jan 2018 — Present · Bengaluru, IN

Education

• Indian Institute of Management Bangalore

  Executive General Management Programme, Business Administration and Management

  2016 — 2017

• NMAMIT Nitte

  Bachelor of Engineering (BE)

• Manipal Academy of Higher Education

  MS, VLSI

Skills

• Specman
• Debugging
• Very-Large-Scale Integration (Vlsi)
• Soc
• Fpga
• Asic
• System on a Chip (Soc)
• Perl
• Embedded Systems
• Systemverilog
• Field-Programmable Gate Arrays (Fpga)
• Functional Verification
• Uvm
• Verilog
• Application-Specific Integrated Circuits (Asic)
• C
• Silicon Validation
• Testing
• Vmm