Shashi Kant Sahu
ASIC Reliability Verification(EM/IR) Engineer|| Interested in EM/IR, Physical Design.
- Role
- Physical Design Engineer at Intel
- Location
- Varanasi, UP, IN
- LinkedIn followers
- 500 followers
About Shashi Kant Sahu
Physical Design | STA & IR/EM | VLSI AutomationI’m a Physical Design Engineer with expertise in RTL to GDSII, STA, and IR/EM analysis across 7nm & 5nm nodes. My work revolves around timing closure, congestion reduction, and power integrity, ensuring efficient and reliable chip designs. Key Focus Areas-Physical Design & STA – Floorplanning, placement, CTS, routing, and timing optimization.IR/EM & Reliability – Power integrity analysis, electromigration, and IR drop mitigation.Automation – TCL/Python scripting to streamline PNR & STA workflows. Experience- Digicomm Semiconductor (1 year): Working on 7nm/5nm Physical Design, timing closure, IR drop optimization. Intel (Internship, 1 year): ASIC Reliability Verification, STA & IR/EM analysis for 5nm/3nm.I’m always eager to learn, collaborate, and explore new ways to enhance chip design efficiency. Let’s connect🤝
Experience
Physical Design Engineer
Apr 2025 — Present · Karnataka, IN
Education
Institute of Engineering and Technology
Bachelor’s Degree, electronics & communication
2015 — 2019
National Institute of Technology, Goa
Master of Technology - MTech, VLSI
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