Shashikanth Reddy
Place and Route ,Power Analysis (PtPx), Synthesis ,ECO, Full chip dynamic power analysis,DPO, DRC, LVS, 3nm 6nm 7nm 14nm 28nm 32nm 40nm ( schematic designs in 45nm, 90nm and 180nm cadence virtuoso )
- Role
- Senior Silicon Design Engineer at AMD
- Location
- Hyderabad, TG, IN
- LinkedIn followers
- 500 followers
About Shashikanth Reddy
Responsibility in Physical Design Execution. working with PNR team and Power team. Strong Domain knowledge in PNR/POWER/ SYNTHESIZE/ECO. Working experience in 3nm 6nm 7nm 14nm 16nm 28nm 32nm 40nm 90nm 180nm Experience in tools, fc_shell,ptpx,dc_shell,icc2_shell, Prime Time, PTDMSA, Genus, Innovous,(virtuoso),icc2_lm_shell,starrc and fusion compiler. Experience in ECOs Responsibility in Handling PNR from RTL to GDSII. Majority IPs worked in DDR, Serdes,NBIO,Data frabic and AI. PTPX power analysis vector based full chip as well as block level. DRC and LVS clean. RDL routing at block level. Bump placement. IO placement. Feed Custom Routing.
Experience
Senior Silicon Design Engineer
Apr 2025 — Present
Place and Route Engineer, Power Analysis (PtPx)
Education
INSTITUTE OF AERONAUTICAL ENGINEERING
Master's Degree, Electrical, Electronic and Communications Engineering Technology/Technician
JNTU Hyderabad
Bachelor's Degree, Electrical, Electronics and Communications Engineering
2009 — 2013
Skills
- Troubleshooting
- Organizational Development
- Web Design
- Microsoft Office
- Youth Development
- Asp.net
- Social Networking
- Microsoft Word
- Team Leadership
- Cadence Virtuoso
- Logistics
- Powerpoint
- Program Management
- Recruiting
- Engineering
- Software Engineering
- Time Management
- Employee Relations
- Embedded Software
- Sales Operations
- Web Services
- Project Management
- Human Resources
- Event Management
- C
- Telecommunications
- Quality Control
- Problem Solving
- Video Editing
- Quality Management
- Teamwork
- Photoshop
- .net
- Software Quality Assurance
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